1. Field of the Invention
The present invention relates to a drive device of a display panel in which light emitting elements constituting pixels are actively driven for example by TFTs (thin film transistors), and more particularly to a drive device and a drive method of a display panel in which display quality of an image which is caused by a ripple component superimposed onto the drive power source of the light emitting elements can be prevented from deteriorating.
2. Description of the Related Art
A display employing a display panel constructed by arranging light emitting elements in a matrix pattern has been developed widely, and as the light emitting element employed in such a display panel, for example, an organic EL (electroluminescent) element in which an organic material is employed in a light emitting layer has attracted attention. This is because of backgrounds one of which is that by employing, in the light emitting layer of the EL element, an organic compound which enables an excellent light emission characteristic to be expected, a high efficiency and a long life which can be equal to practical use have been advanced.
As the display panel employing such organic EL elements, a simple matrix type display panel in which EL elements are arranged simply in a matrix pattern and an active matrix type display panel in which active elements constituted by the above-mentioned TFTs are added to respective EL elements which are arranged in a matrix pattern have been proposed. The latter active matrix type display panel can realize a low power consumption, compared to the former simple matrix type display panel, and has characteristics such as less cross talk among pixels or the like, thereby being suitable for a high definition display specifically constituting a large screen.
FIG. 1 shows one example of a basic circuit structure corresponding to one pixel and its circuit in a conventional active matrix type display panel and a power supply circuit supplying a drive power source to the display panel in which a large number of the pixels are provided. In the display panel 1 the circuit structure of one pixel 2 is shown for convenience of illustration, and this circuit structure of the pixel 2 shows a most basic pixel structure of a case of a so-called conductance controlled method where the organic EL elements are employed as light emitting elements.
That is, gate electrode (hereinafter simply referred to as gate) of an N-channel type scan selection transistor Tr1 constituted by a TFT is connected to a scan selection line (scan line A1), and source electrode (hereinafter simply referred to as source) is connected to a data line (data line B1). Drain electrode (hereinafter simply referred to as drain) of this scan selection transistor Tr1 is connected to the gate of a P-channel type light emission drive transistor Tr2 and to one terminal of a charge-holding capacitor Cs.
The source of the light emission drive transistor Tr2 is connected to the other terminal of the capacitor Cs and receives supply of a drive power source Va (hereinafter referred to also as drive voltage Va) from a later-described DC-DC converter via a power supply line P1 arranged in the display panel 1. The drain of the light emission drive transistor Tr2 is connected to the anode terminal of an organic EL element E1, and the cathode terminal of this organic EL element E1 is connected to a reference potential point (ground) in the example shown in FIG. 1.
In the circuit structure of the pixel 2, when a select voltage Select is supplied to the gate of the scan selection transistor Tr1 via the scan line A1 during an address period (data writing period), the scan selection transistor Tr1 becomes in an ON state. Upon receiving a data voltage Vdata which corresponds to a write data from the data line B1 supplied to the source of the scan selection transistor Tr1, the scan selection transistor Tr1 allows current corresponding to the data voltage Vdata to flow from the source to the drain. Accordingly, during the period in which the selection voltage Select is applied to the gate of the transistor Tr1, the capacitor Cs is charged, and the charge voltage thereof corresponds to the data voltage Vdata.
Meanwhile, the charge voltage created by charging in the capacitor Cs is supplied to the light emission drive transistor Tr2 as the gate voltage, current based on that gate voltage and the drive voltage Va supplied to the light emission drive transistor Tr2 via the power supply line P1 that is the source voltage flows from the drain to the EL element E1, and the EL element E1 is driven to emit light by the drain current of the light emission drive transistor Tr2.
Here, an addressing operation corresponding to one scan line is completed, and when the gate voltage of the scan selection transistor Tr1 becomes an OFF voltage, this transistor Tr1 becomes so-called cutoff, whereby the drain side of the transistor Tr1 becomes in an open state. However, in the light emission drive transistor Tr2 the gate voltage is maintained by electrical charge accumulated in the capacitor Cs, and the same drive current is maintained until the data voltage Vdata is rewritten during a next address period, whereby the light emission state of the EL element E1 based on this drive current is also maintained.
A large number of the constructions of the pixels 2 described above are arranged in a matrix pattern in the display panel 1 shown in FIG. 1 to construct a dot matrix type display panel, and the respective pixels 2 are respectively formed at crossing positions between respective scan lines A1, . . . and respective data lines B1 . . .
A video signal displayed in the light emitting display panel 2 is supplied to a light emission control circuit 4 shown in FIG. 1. This light emission control circuit 4 converts an input video signal to corresponding pixel data for each one pixel by performing a sampling process or the like based on horizontal and vertical synchronization signals in the video signal and implements a writing operation in which the data is written in an illustrated frame memory sequentially. During the address period after the writing operation for one frame pixel data written in the frame memory is completed, the serial pixel data read out of the frame memory for each one scan line and shift lock signal are sequentially supplied to a shift register and data latch circuit 5a in a data driver 5.
This shift register and data latch circuit 5a operate to incorporate and latch pixel data corresponding to one horizontal scan, utilizing the above-mentioned shift lock signal, and to supply latch output corresponding to one horizontal scan to a level shifter 5b as parallel data. By this operation, the data voltage Vdata corresponding to the pixel data is respectively supplied to the source of the scan selection transistor Tr1 constituting each pixel 2. Such an operation is repeated for each one scan during the address period.
A scan clock signal corresponding to the horizontal synchronization signal is supplied from the light emission control circuit 4 to a scan driver 6 during the address period. This scan clock signal is supplied to a shift register 6a so as to operate to generate a register output sequentially. The register output is converted into a predetermined operation level by a level shifter 6b and is output to the respective scan lines A1, . . . By this operation, the selection voltage Select is sequentially supplied to the gate of the scan selection transistor Tr1 constituting each pixel 2 for each scan line.
Accordingly, the respective pixels 2 on the display panel 1 arranged on the scan line receive supply of the selection voltage Select from the scan driver 6 for each one scan of the address period. In synchronization with this, the data voltage Vdata is supplied form the level shifter 5b in the data driver 5 to the respective pixels 2 arranged for each scan line, and the gate voltage corresponding to the data voltage Vdata is respectively written in the respective pixels (that is, the capacitors Cs) which correspond to this scan line. This operation is executed for the all scan lines so that an image corresponding to one frame is reproduced on the display panel 1.
Meanwhile, the drive voltage Va by the DC-DC converter designated by reference numeral 8 is supplied to the respective pixels 2 arranged in the display panel 1 via the power lines P1 . . . . In the structure shown in this FIG. 1, the DC-DC converter 8 utilizes PWM (pulse width modulation) control to operate to boost the output voltage of a DC voltage source Ba of the primary side.
This DC-DC converter 8 is constructed such that a PWM wave output from a switching regulator circuit 9 performs ON control for a MOS type power FET Q1 provided as a switching element at a predetermined duty cycle. That is, by the ON operation of the power FET Q1, electrical energy from the DC voltage source Ba of the primary side is accumulated in an inductor L1, and the electrical energy accumulated in the inductor L1 is accumulated in a smoothing capacitor C1 via a diode D1, accompanied by an OFF operation of the power FET Q1. By repeats of the ON and OFF operations of the power FET Q1, a boosted DC output can be obtained as a terminal voltage of the capacitor C1.
The DC output voltage is divided by a thermistor TH1 performing temperature compensation and resistances R11 and R12, is supplied to an error amplifier 10 in the switching regulator circuit 9, and is compared to a reference voltage Vref in this error amplifier 10. This comparison output (error output) is supplied to a PWM circuit 11, and by controlling the duty of a signal wave provided from an oscillator 12, the output voltage is feedback controlled so as to be maintained at a predetermined drive voltage Va. Therefore, the output voltage by the DC-DC converter, that is, the drive voltage Va, can be shown as the following Equation 1:Va=Vref×[(TH1+R11+R12)/R12]  (Equation 1)
The construction of the pixel structure and the drive circuit therefore as shown in FIG. 1 is disclosed in Japanese Patent Application Laid-Open No. 2003-316315 that the present applicant has already filed, and the DC-DC converter as shown in FIG. 1 is disclosed in Japanese Patent Application Laid-Open No. 2002-366101 that the present applicant has already filed.
Meanwhile, in the structure of the pixel 2 shown in FIG. 1, a drain current Id which drives and allows the organic EL element E1 to emit light is determined by the error (gate-to-source voltage=Vgs of the transistor Tr2) between the drive voltage Va supplied via the power line P1 and the gate voltage of the drive transistor Tr2 which is determined by electrical charge accumulated in the capacitor Cs. FIG. 2 shows an equivalent circuit of the pixel structure, wherein the already explained scan selection transistor Tr1 is replaced and shown by a switch SW1. In FIG. 2, the data voltage Vdata transmitted via the data line B1 is equivalently shown by a gate voltage Vgate by means of a variable voltage source.
Here, for the drive voltage Va supplied to the source of the transistor Tr2, the boosted voltage by the DC-DC converter is employed as already described, and in this type of DC-DC converter, it is unavoidable that ripple noise (ripple component) is superimposed on the voltage Va to some degree since switching operation is accompanied as a matter of its operating principle. In the DC-DC converter, although the level of the ripple component can be decreased more when a large capacitance capacitor is used for the smoothing capacitor C1, decrease effect for the ripple component cannot be expected so much compared to the ratio at which the capacitance thereof is increased.
Particularly, although the demand for the display panel and the DC-DC converter driving this display panel which are shown in FIG. 1 is increasing due to the spread of cellular phones, personal digital assistants (PDAs), and the like, employing a large capacitance smoothing capacitor for this type of equipment not only increases the cost but also increases the occupying volume of the capacitor. Thus, restriction on design that the capacitance of the smoothing capacitor has to be restrained to some degree exists in an actual condition.
Therefore, in the equivalent circuit shown in FIG. 2, the drive voltage Va on which the ripple component shown in FIG. 3 is superimposed is supplied to the source of the light emission drive transistor Tr2. Meanwhile, the switch SW1 is turned on at the addressing time (data write time), and the gate voltage Vgate based on the video signal is supplied to the gate of the drive transistor Tr2. Therefore, a gate-to-source voltage which changes corresponding to the ripple component is supplied between the source and the gate of the transistor Tr2 shown in FIG. 2, in response to respective timings of addressing, as shown as Vgs1, Vgs2, Vgs3 in FIG. 3.
FIG. 4 shows a Vgs/Id characteristic (a gate-to-source voltage versus drain current characteristic) of a TFT, represented by the transistor Tr2, and when the gate-to-source voltage changes within a range of Δvgs, accompanied by this, the drain current also changes within a range of ΔId. Here, it has been known that the organic EL element exhibits a light emission intensity characteristic approximately proportional to the value of the current flowing in this element. Accordingly, as a result of the state in which Vgs changes influenced by the ripple component corresponding to timings of addressing as described above, a result in which the light emission intensity of each EL element in the light emitting display panel 1 differs for each scan line occurs. Thus, in the display panel, a problem that the display quality of an image is considerably deteriorated, that is, for example, a fine striped pattern or phenomenon of flicker occurs and the like, can occur.
In order to avoid such a problem, it can be considered that a regulator circuit for example as shown in FIG. 5 is adopted. That is, the regulator circuit shown in FIG. 5 is interposed between the output terminal of the DC-DC converter and the power supply lines P1, . . . in the display panel 1. The regulator circuit shown in this FIG. 5 is composed of an NPN transistor Q2, an error amplifier constituted by an operational amplifier OP1, and a reference voltage source Vref1. The emitter potential of the NPN transistor Q2 is supplied to the noninverting input terminal of the operational amplifier OP1, and the electrical potential of the reference voltage source Vref1 is supplied to the inverting input terminal of the operational amplifier OP1.
With this structure, the ripple component generated in the emitter side of the transistor Q2 is output to the error amplifier constituted by the operational amplifier OP1. Since the base potential of the transistor Q2 is changed by the output of the error amplifier, as a result, at the emitter side of the transistor Q2, that is, at Vout side, an output voltage in which the ripple component is almost removed can be obtained. However, in the regulator circuit, a power loss of (Vin−Vout)×Iout=P[W] always occurs. Accordingly, due to a problem that the continuous utilization time of a battery is drastically shortened, it is difficult to adopt such a device in the above-mentioned portable equipment under actual conditions.